ISL90842WIV1427Z-TK 데이터 시트보기 (PDF) - Intersil
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ISL90842WIV1427Z-TK Datasheet PDF : 10 Pages
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ISL90842
SIGNALS
FROM THE
MASTER
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W=0
ADDRESS
BYTE
S
T
A IDENTIFICATION
R BYTE WITH
T
R/W=1
A
A
C
C
K
K
S
T
O
P
SIGNAL AT SDA 0 1 0 1 0 A1A0 0 0 0 0 0 0 0
A
SIGNALS FROM
C
THE SLAVE
K
0 1 0 1 0 A1A0 1
A
A
C
C FIRST READ
K
K DATA BYTE
FIGURE 12. READ SEQUENCE
LAST READ
DATA BYTE
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL90842 responds with an ACK. At this time, the device
enters its standby state (See Figure 11).
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 12). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL90842 responds with an ACK. Then the ISL90842
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a
STOP condition) following the last bit of the last Data Byte
(See Figure 12).
The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 03h the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
9
FN8096.1
January 16, 2006
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