ISL8502 데이터 시트보기 (PDF) - Intersil
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ISL8502 Datasheet PDF : 19 Pages
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ISL8502
a voltage rating of 1.5x is a conservative guideline. For most
cases, the RMS current rating requirement for the input
capacitor of a buck regulator is approximately 1/2 the DC
load current.
The maximum RMS current through the input capacitors
may be closely approximated using Equation 10:
V-----O----U---T-
VIN
×
⎛
⎜
⎝
IO
U
TMA
2
X
×
⎝⎛1
–
V---V--O--I--UN---T-⎠⎞
+
--1----
12
×
⎛
⎜
⎝
V-----I-N-----–-----V----O----U---T-
L × fOSC
×
-V--V--O--I--UN---T-⎠⎟⎞
2⎞
⎟
⎠
(EQ. 10)
For a through-hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
Feedback Compensation
Figure 34 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The error
amplifier output (VE/A) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the PHASE node. The
PWM wave is smoothed by the output filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR. The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage DVOSC. The ISL8502
incorporates a feed forward loop that accounts for changes
in the input voltage. This maintains a constant modulator
gain.
OSC
PWM
COMPARATOR
-
Δ VOSC
+
DRIVER
DRIVER
VIN
LO
PHASE CO
VOUT
ZFB
VE/A
-
+
ZIN
ERROR REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C1
C2
R2
ZFB
VOUT
ZIN
C3 R3
COMP
R1
FB
-
+
R4
ISL8502
REFERENCE
VOUT
=
0.6
×
⎛
⎜
⎝
1
+
RR-----14- ⎠⎟⎞
FIGURE 34. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
Modulator Break Frequency Equations
fLC=
---------------------1---------------------
2π x LO x CO
fESR= 2----π------x-----E----S--1---R------x-----C-----O---
(EQ. 11)
The compensation network consists of the error amplifier
(internal to the ISL8502) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f0dB and
180°. Equation 12 relates the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2 and
C3) in Figure 34. Use these guidelines for locating the poles
and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth.
2. Place 1st Zero Below Filter’s Double Pole (~75% FLC).
3. Place 2nd Zero at Filter’s Double Pole.
4. Place 1st Pole at the ESR Zero.
5. Place 2nd Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
16
FN6389.2
June 29, 2010
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