ISL80102IR33Z-T 데이터 시트보기 (PDF) - Intersil

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ISL80102IR33Z-T

High Performance 2A and 3A Linear Regulators

Intersil 

Pin Configuration

ISL80102, ISL80103

ISL80102, ISL80103

(10 LD 3X3 DFN)

TOP VIEW

VOUT 1

VOUT 2

SENSE/ADJ 3

PG 4

GND 5

10 VIN

9 VIN

8 DNC

7 ENABLE

6 SS

Pin Descriptions

PIN NUMBER PIN NAME

DESCRIPTION

1, 2

3

4

VOUT

Output voltage pin.

SENSE/ADJ Remote voltage sense for internally fixed VOUT options. ADJ pin for externally set VOUT.

PG

VOUT in regulation signal. Logic low defines when VOUT is not in regulation. Must be grounded if

not used.

5

GND

GND pin.

6

SS

External cap adjusts in-rush current.

7

ENABLE VIN independent chip enable. TTL and CMOS compatible.

8

DNC

Do not connect this pin to ground or supply. Leave floating.

9, 10

VIN

EPAD

Input supply pin.

EPAD at ground potential. Soldering it directly to GND plane is optional.

Typical Application

ISL80102, ISL80103

2.5V ±10%

VIN

R1

10kΩ

CIN

10µF

EN

OPEN DRAIN COMPATIBLE

*CSS

9

VIN

10

VIN

7

ENABLE

6

SS

GND

5

1

VOUT

2

VOUT

COUT

10µF

4

PG

ADJ 3

**CPB

1500pF

*CSS is optional, (see Note 12) on page 5.

**CPB is optional. See “Functional Description” on page 12 for more information.

FIGURE 1. TYPICAL APPLICATION DIAGRAM

1.8V

VOUT

RPG

100kΩ

PGOOD

R3

2.61kΩ

R4

1.0kΩ

3

FN6660.1

March 22, 2010

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