SAA7186 데이터 시트보기 (PDF) - Philips Electronics

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SAA7186

Digital video scaler

Philips Electronics 

Philips Semiconductors

Digital video scaler

Preliminary specification

SAA7186

shorter than XS, processing is aborted when the falling

edge of HREF is detected.

Vertical regions in Fig.4:

• the two regions can be programmed via I2C-bus,

whereby regions should not overlap (active region

overrides the bypass region).

• the start of a normal active picture depends on video

standard and has to be programmed to the correct

value.

• the offsets XO and YO have to be set according to the

internal processing delays to ensure the complete

number of destination pixels and lines (Table 6).

• the scaling parameters can be used to perform a

panning function over the video frame/field.

handbook, full pagewidth

LLC

CREF

HREF

Byte numbers for pixles:

Y signal

U and V signal

start of

active line

0

1

2

3

4

5

6

7

U0

V0

U2

V2

U4

V4

U6

V6

MEH411

handbook, full pagewidth

LLC

CREF

HREF

Byte number for pixels:

Y signal

n–5

U and V signal

Un-5

n–4

Vn-5

n–3

Un-3

n–2

Vn-3

end of

active line

n–1

n

Un-1

Vn-1

May 1993

Fig.3 Horizontal and data multiplex timing.

11

MEH410

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