ISL6265HRTZ-T 데이터 시트보기 (PDF) - Intersil

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ISL6265HRTZ-T

Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

Intersil 

ISL6265

Electrical Specifications

VCC = PVCC = 5V, VIN = 12V, TA = -10°C to +100°C; Parameters with MIN and/or MAX limits are 100% tested

at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production

tested. (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN TYP MAX UNITS

OFFSET FUNCTION

OFS Pin Voltage For Droop Enabling

FB Pin Source Current

OFS Pin Voltage Threshold for VFIX

Mode and No Droop Operation (Note 3)

VOFS

IFB

VOFS

ROFS = 240kΩ (OFS pin to GND)

IOFS = 10µA

1.18 1.2 1.22 V

9.0 9.9 10.8 µA

-

1.8

-

V

OFS Pin Voltage Threshold for SVI Mode

and No Droop Operation (Note 3)

VOFS

-

4.0

-

V

OFS Bias (Note 3)

LOGIC INPUTS

IOFS

1.8V < OFS < VCC

-

4.0

-

µA

ENABLE Low Threshold

ENABLE High Threshold

ENABLE Leakage Current

VIL(3.3V)

VIH(3.3V)

Logic input is low

- 1.35 0.9

V

2.0 1.6

-

V

-1

0

-

µA

Logic input is high at 3.3V

-

0

1

µA

SVI INTERFACE

PWROK Input Low Threshold

- 0.65 0.8

V

PWROK Input High Threshold (Note 3)

-

0.9

-

V

SVC, SVD Input HIGH (VIH)

1.05 0.87 -

V

SVC, SVD Input LOW (VIL)

- 0.68 0.45 V

Schmitt Trigger Input Hysteresis (Note 3)

- 0.19 -

V

SVD Low Level Output Voltage

3mA Sink Current

-

0.1 0.285 V

SVC, SVD Leakage (Note 3)

EN = 0V, SVC, SVD = 0V

- < -100 -

nA

EN = 5V, SVC, SVD = 1.8V

- < -100 -

nA

DIFF AMP

Accuracy

VSEN = 0.5V to 1.55V; RTN = 0 ±0.1V

-2

-

2

mV

NOTES:

3. Limits should be considered typical and are not production tested.

4. Limits established by characterization and are not production tested.

ISL6265 Gate Driver Timing Diagram

PWM

UGATE

tPDHU

tRU

LGATE

1V

tFL

tFU

1V

tRL

tPDHL

8

FN6599.1

May 13, 2009

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