6130IRZ(2011) 데이터 시트보기 (PDF) - Intersil
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6130IRZ Datasheet PDF : 23 Pages
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ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
If some of the rails are sequenced together to reduce cost and
eliminate the effect of capacitor variance on the timing, a
common capacitor can be connected to two or more DLY_ON or
DLY_OFF pins. In this case, multiply the capacitor value by the
number of common DLY_X pins to obtain the desired timing.
Table 1 shows the nominal time delay on the DLY_X pins for
various capacitor values, from the start of charging to the 1.27V
reference. This table does not include the 10ms of ENABLE
lockout delay during a start-up sequence, but it does represent
the time from the end of the ENABLE lockout delay to the start
of GATE transition. There is no ENABLE lockout delay for a
sequence-off, so this table illustrates the delay to GATE
transition from a disable signal.
TABLE 1. NOMINAL DELAY TO SEQUENCING THRESHOLD
DLY PIN CAPACITANCE
TIME(s)
Open
0.00006
100pF
0.00013
1000pF
0.0013
0.01µF
0.013
0.1µF
0.13
1µF
1.3
10µF
13
NOTE: Nom. TDEL_SEQ = Capacitor (µF)*1.3MΩ.
Figure 4 shows the turn-on and Figure 5 shows the nominal
turn-off timing diagram of the ISL6123 and ISL6124.
The ISL6125 is similar to the ISL6124 except that, instead of
charge pumped GATE outputs, there are sequenced open-drain
outputs that can be pulled up to a maximum of VDD.
Delay and flexible sequencing possibilities include multiple series,
parallel, or adjustable capacitors that can be used to easily
fine-tune timing over that offered by standard value capacitors.
UVLO_A
UVLO_B
UVLO_C
UVLO_D
ENABLE (ISL6124)
ENABLE (ISL6123)
DLYON_B
DLYON_D
DLYON_A
DLYON_C
VUVLOVth
VUVLOVth
VUVLOVth
VUVLOVth
tUVLOdel
VEN
DLY_Vth
DLY_Vth
DLY_Vth
DLY_Vth
<tFIL
GATE_B
GATE_D
GATE_C
GATE_A
VQPUMP-1V
tRSTdel
RESET
FIGURE 4. ISL6123, ISL6124 TURN-ON AND GLITCH RESPONSE TIMING DIAGRAM
VQPUMP
VQPUMP
VQPUMP
VQPUMP
9
FN9005.11
August 25, 2011
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