IS62WV2568BLL-70H 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS62WV2568BLL-70H

256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

Integrated Silicon Solution 

IS62WV2568ALL, IS62WV2568BLL

ISSI ®

READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)

Symbol

Parameter

55 ns

70 ns

Min. Max.

Min. Max.

Unit

tRC

Read Cycle Time

55

—

70

—

ns

tAA

Address Access Time

—

55

—

70

ns

tOHA

Output Hold Time

10

—

10

—

ns

tACS1/tACS2

CS1/CS2 Access Time

—

55

—

70

ns

tDOE

OE Access Time

—

25

—

35

ns

tHZOE(2)

OE to High-Z Output

—

20

—

25

ns

tLZOE(2)

OE to Low-Z Output

5

—

5

—

ns

t t HZCS1/ HZCS2(2) CS1/CS2 to High-Z Output

0

20

0

25

ns

t t LZCS1/ LZCS2(2) CS1/CS2 to Low-Z Output

10

—

10

—

ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V

and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

AC WAVEFORMS

READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH)

ADDRESS

DOUT

tRC

tAA

tOHA

PREVIOUS DATA VALID

tOHA

DATA VALID

6

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. B

06/20/05

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