IS62WV5128ALL-70H 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS62WV5128ALL-70H

512K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

Integrated Silicon Solution 

IS62WV5128ALL, IS62WV5128BLL

ISSI ®

WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)

Symbol

tWC

tSCS1

tAW

tHA

tSA

tPWE

tSD

tHD

tHZWE(3)

tLZWE(3)

Parameter

Write Cycle Time

CS1 to Write End

Address Setup Time to Write End

Address Hold from Write End

Address Setup Time

WE Pulse Width

Data Setup to Write End

Data Hold from Write End

WE LOW to High-Z Output

WE HIGH to Low-Z Output

55 ns

Min. Max.

55 —

45

—

45

—

0

—

0

—

40

—

25

—

0

—

— 20

5

—

70 ns

Min. Max.

Unit

70 —

ns

60 —

ns

60 —

ns

0—

ns

0—

ns

50 —

ns

30 —

ns

0—

ns

— 20

ns

5—

ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to

VDD-0.2V/VDD-0.3V and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of CS1 LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to

terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

AC WAVEFORMS

WRITE CYCLE NO. 1 (CS1 Controlled, OE = HIGH or LOW)

ADDRESS

CS1

tWC

tSCS1

tHA

WE

DOUT

DIN

tAW

tPWE

tSA

tHZWE

DATA UNDEFINED

HIGH-Z

tLZWE

tSD

tHD

DATA-IN VALID

8

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. A

04/30/03

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