IS62WV12816 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS62WV12816

128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

Integrated Silicon Solution 

IS62WV12816ALL, IS62WV12816BLL

ISSI ®

WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)

Symbol Parameter

tWC

Write Cycle Time

tSCS1/tSCS2 CS1/CS2 to Write End

tAW

Address Setup Time to Write End

tHA

Address Hold from Write End

tSA

Address Setup Time

tPWB

LB, UB Valid to End of Write

tPWE

WE Pulse Width

tSD

Data Setup to Write End

tHD

Data Hold from Write End

tHZWE(3) WE LOW to High-Z Output

tLZWE(3) WE HIGH to Low-Z Output

45ns

Min. Max.

45 —

35 —

35 —

0—

0—

35 —

35 —

20 —

0—

— 20

5—

55 ns

Min. Max.

55 —

45 —

45 —

0—

0—

45 —

40 —

25 —

0—

— 20

5—

70 ns

Min. Max.

Unit

70 —

ns

60 —

ns

60 —

ns

0—

ns

0—

ns

60 —

ns

50 —

ns

30 —

ns

0—

ns

— 20

ns

5—

ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V

and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but

any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the

write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

9

Rev. E

06/08/05

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