IS62C1024 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS62C1024

128K x 8 HIGH-SPEED CMOS STATIC RAM

Integrated Silicon Solution 

IS62C1024

AC WAVEFORMS

WRITE CYCLE NO. 1 (WE Controlled)(1,2)

ADDRESS

CE1

CE2

WE

DOUT

DIN

tWC

tSCE1

tHA

tSCE2

tAW

tPWE(4)

tSA

tHZWE

DATA UNDEFINED

HIGH-Z

tLZWE

tSD

tHD

DATA-IN VALID

ISSI ®

WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)

ADDRESS

CE1

CE2

WE

DOUT

DIN

tWC

tSA

tSCE1

tHA

tSCE2

tAW

tPWE(4)

tHZWE

DATA UNDEFINED

HIGH-Z

tLZWE

tSD

tHD

DATA-IN VALID

Notes:

1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if OE = VIH.

Integrated Silicon Solution, Inc. — 1-800-379-4774

7

Rev. G

01/14/00

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