IS61NVF12836A-7.5B3 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS61NVF12836A-7.5B3

128K x 36 and 256K x 18 4Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM

Integrated Silicon Solution 

IS61NLF12836A/IS61NVF12836A

IS61NLF25618A/IS61NVF25618A

ASYNCHRONOUS TRUTH TABLE(1)

Operation

ZZ

OE

I/O STATUS

Sleep Mode

H

X

High-Z

Read

L

L

L

H

DQ

High-Z

Write

L

X

Din, High-Z

Deselected

L

X

High-Z

Notes:

1. X means "Don't Care".

2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus

contention will occur.

3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.

4. Deselected means power Sleep Mode where stand-by current depends on cycle time.

WRITE TRUTH TABLE (x18)

Operation

WE

BWa

BWb

READ

H

X

X

WRITE BYTE a

L

L

H

WRITE BYTE b

L

H

L

WRITE ALL BYTEs

L

L

L

WRITE ABORT/NOP

L

H

H

Notes:

1. X means "Don't Care".

2. All inputs in this table must beet setup and hold time around the rising edge of CLK.

ISSI ®

10

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. 00A

08/26/05

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