IS61NLP12836A-200B2I 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS61NLP12836A-200B2I

128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

Integrated Silicon Solution 

IS61NLP12832A

IS61NLP12836A/IS61NVP12836A

IS61NLP25618A/IS61NVP25618A

ISSI ®

119-PIN PBGA PACKAGE CONFIGURATION 128K x 36 (TOP VIEW)

1

2

3

4

5

6

7

A

VDDQ

A

A

B

NC

CE2

A

C

NC

A

A

NC

ADV

VDD

A

A

VDDQ

A

CE2

NC

A

A

NC

D DQc

DQPc

VSS

NC

Vss

DQPb DQb

E DQc

DQc

VSS

CE

Vss

DQb DQb

F

VDDQ

DQc

VSS

OE

Vss

DQb

VDDQ

G DQc

H DQc

J

VDDQ

K DQd

L DQd

M

VDDQ

DQc

DQc

VDD

DQd

DQd

DQd

BWc

VSS

NC

VSS

BWd

VSS

NC

WE

VDD

CLK

NC

CKE

BWb

Vss

NC

Vss

BWa

Vss

DQb

DQb

VDD

DQa

DQa

DQa

DQb

DQb

VDDQ

DQa

DQa

VDDQ

N DQd

DQd

VSS

A1*

Vss

DQa DQa

P DQd

DQPd

VSS

A0*

Vss

DQPa DQa

R

NC

A

MODE

VDD

NC

A

NC

T

NC

NC

A

A

A

NC

ZZ

U VDDQ

NC

NC

NC

NC

NC

VDDQ

Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

Symbol

A

A0, A1

ADV

WE

CLK

CKE

CE

CE2

CE2

BWx (x=a-d)

Pin Name

Address Inputs

Synchronous Burst Address Inputs

Synchronous Burst Address Advance/

Load

Synchronous Read/Write Control Input

Synchronous Clock

Clock Enable

Synchronous Chip Select

Synchronous Chip Select

Synchronous Chip Select

Synchronous Byte Write Inputs

OE

ZZ

MODE

VDD

VSS

NC

DQa-DQd

DQPa-Pd

VDDQ

Output Enable

Power Sleep Mode

Burst Sequence Selection

Power Supply

Ground

No Connect

Data Inputs/Outputs

Parity Data I/O

Output Power Supply

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

5

Rev. 00C

09/12/05

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