IS61NLP25636A-200B2 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS61NLP25636A-200B2

256K x 36 and 512K x 18 9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

Integrated Silicon Solution 

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218A

ASYNCHRONOUS TRUTH TABLE(1)

Operation

ZZ

OE

I/O STATUS

Sleep Mode

H

X

High-Z

Read

L

L

L

H

DQ

High-Z

Write

L

X

Din, High-Z

Deselected

L

X

High-Z

Notes:

1. X means "Don't Care".

2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus

contention will occur.

3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.

4. Deselected means power Sleep Mode where stand-by current depends on cycle time.

ISSI ®

WRITE TRUTH TABLE (x18)

Operation

WE

BWa

BWb

READ

H

X

X

WRITE BYTE a

L

L

H

WRITE BYTE b

L

H

L

WRITE ALL BYTEs

L

L

L

WRITE ABORT/NOP

L

H

H

Notes:

1. X means "Don't Care".

2. All inputs in this table must beet setup and hold time around the rising edge of CLK.

10

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. B

06/27/06

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