IS61LPS12832A-200TQ 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS61LPS12832A-200TQ

128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

Integrated Silicon Solution 

IS61(64)LPS12832A

IS61(64)LPS12836A IS61(64)VPS12836A

IS61(64)LPS25618A IS61(64)VPS25618A

INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)

External Address

A1 A0

1st Burst Address

A1 A0

2nd Burst Address

A1 A0

3rd Burst Address

A1 A0

00

01

10

11

01

00

11

10

10

11

00

01

11

10

01

00

ISSI ®

LINEAR BURST ADDRESS TABLE (MODE = VSS)

0,0

A1', A0' = 1,1

0,1

1,0

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameter

TSTG

Storage Temperature

PD

Power Dissipation

IOUT

Output Current (per I/O)

VIN, VOUT Voltage Relative to Vss for I/O Pins

VIN

Voltage Relative to Vss for

for Address and Control Inputs

Value

–55 to +150

1.6

100

–0.5 to VDDQ + 0.5

–0.5 to VDD + 0.5

Unit

°C

W

mA

V

V

VDD

Voltage on VDD Supply Relative to Vss

–0.5 to 4.6

V

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-

nent damage to the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

2. This device contains circuity to protect the inputs against damage due to high static voltages or

electric fields; however, precautions may be taken to avoid application of any voltage higher than

maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.

Integrated Silicon Solution, Inc. — 1-800-379-4774

11

Rev. 00A

10/07/04

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