IS61C1024 데이터 시트보기 (PDF) - Integrated Silicon Solution
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IS61C1024 Datasheet PDF : 10 Pages
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IS61C1024
IS61C1024L
128K x 8 HIGH-SPEED
CMOS STATIC RAM
ISSI ®
MAY 1999
FEATURES
• High-speed access time: 12, 15, 20, 25 ns
• Low active power: 600 mW (typical)
• Low standby power: 500 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
• Low power version available: IS61C1024L
• Commercial and industrial temperature ranges
available
DESCRIPTION
The ISSI IS61C1024 and IS61C1024L are very high-speed,
low power, 131,072-word by 8-bit CMOS static RAMs. They
are fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with innovative
circuit design techniques, yields higher performance and low
power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS61C1024 and IS61C1024L are available in 32-pin
300-mil SOJ, and TSOP (Type I, 8x20), and sTSOP (Type I,
8 x 13.4) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
VCC
GND
I/O0-I/O7
DECODER
I/O
DATA
CIRCUIT
512 x 2048
MEMORY ARRAY
COLUMN I/O
CE1
CE2
CONTROL
OE
CIRCUIT
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
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1
SR028-1K
05/12/99
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