INTEL387TMDX 데이터 시트보기 (PDF) - Intel

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INTEL387TMDX

Intel387™ DX MATH COPROCESSOR

Intel 

Intel387TM DX MATH COPROCESSOR

3 1 1 Intel386TM DX CPU CLOCK 2 (CPUCLK2)

This input uses the Intel386 DX CPU CLK2 signal to

time the bus control logic Several other MCP sig-

nals are referenced to the rising edge of this signal

When CKM e 1 (synchronous mode) this pin also

clocks the data interface and control unit and the

floating-point unit of the MCP This pin requires

MOS-level input The signal on this pin is divided by

two to produce the internal clock signal CLK

3 1 2 Intel387TM DX MCP CLOCK 2 (NUMCLK2)

When CKM e 0 (asynchronous mode) this pin pro-

vides the clock for the data interface and control unit

and the floating-point unit of the MCP In this case

the ratio of the frequency of NUMCLK2 to the fre-

quency of CPUCLK2 must lie within the range 10 16

to 14 10 When CKM e 1 (synchronous mode) this

pin is ignored CPUCLK2 is used instead for the data

interface and control unit and the floating-point unit

This pin requires TTL-level input

3 1 3 Intel387TM DX MCP CLOCKING MODE

(CKM)

This pin is a strapping option When it is strapped to

VCC the MCP operates in synchronous mode when

strapped to VSS the MCP operates in asynchronous

mode These modes relate to clocking of the data

interface and control unit and the floating-point unit

only the bus control logic always operates synchro-

nously with respect to the Intel386 DX Microproces-

sor

Figure 3 2 Asynchronous Operation

240448 – 7

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