IN74ACT163 데이터 시트보기 (PDF) - IK Semicon Co., Ltd
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IN74ACT163 Datasheet PDF : 8 Pages
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IN74ACT163
AC ELECTRICAL CHARACTERISTICS (VCC=5V±10% CL=50pF,Input tr=tf=3.0 ns)
Symbol
Parameter
fmax Maximum Clock Frequency (Figure 1)
tPLH Propagation Delay Clock to Q (Figure 1)
tPHL Propagation Delay Clock to Q (Figure 1)
tPLH Propagation Delay, Clock to Ripple Cary Out
(Figure 1)
tPHL Propagation Delay, Clock to Ripple Cary Out
(Figure 1)
tPLH Propagation Delay, Enable T to Ripple Carry
Out (Figure 2)
tPHL Propagation Delay, Enable T to Ripple Carry
Out (Figure 2)
CIN Maximum Input Capacitance
Guaranteed Limits
25 °C
-40°C to 85°C
Min
Max Min Max
120
105
1.5
10.0 1.5 11.0
1.5
11.0 1.5 12.0
2.5
11.5 2.0 13.5
3.0
13.5 2.0 15.0
2.0
9.0 1.5 10.5
2.0
10.0 2.0 11.0
4.5
4.5
Unit
MHz
ns
ns
ns
ns
ns
ns
pF
CPD Power Dissipation Capacitance
Typical @25°C,VCC=5.0 V
45
pF
TIMING REQUIREMENTS (VCC=5.0V±10%, CL=50pF, Input tr=tf=3.0 ns)
Guaranteed Limit
Symbol
Parameter
+25° C
-40° C
Unit
to +85° C
tsu
Minimum Setup Time, Preset Data Inputs to Clock
10.0
12.0
ns
(Figure 4)
th
Minimum Hold Time, Clock to Preset Data Inputs
0.5
0.5
ns
(Figure 4)
tsu
Minimum Setup Time, Reset to Clock (Figure 3)
10.0
11.5
ns
th
Minimum Hold Time, Clock to Reset (Figure 3)
-0.5
-0.5
ns
tsu
Minimum Setup Time, Load to Clock (Figure 5)
8.5
10.5
ns
th
Minimum Hold Time, Clock to Load or Preset Data
-0.5
Inputs (Figure 5)
0
ns
tsu
Minimum Setup Time, Enable T or Enable P to Clock
5.5
(Figure 5)
6.5
ns
th
Minimum Hold Time, Clock to Enable T or Enable P
0
(Figure 5)
0.5
ns
tw
Minimum Pulse Width, (Load) (Figure 3)
3.5
3.5
ns
tw
Minimum Pulse Width, (Count) (Figure 3)
3.5
3.5
ns
Rev. 00
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