IN74ACT323 데이터 시트보기 (PDF) - IK Semicon Co., Ltd
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IN74ACT323 Datasheet PDF : 8 Pages
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IN74ACT323
AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits
Symbol
Parameter
25 °C
-40°C to 85°C
Min Max Min Max
fmax Maximum Clock Frequency (Figure 1)
120
110
tPLH Propagation Delay, Clock to QA’ or QH’ (Figure 1) 5.0 12.5 4.0 14.0
tPHL Propagation Delay, Clock to QA’ or QH’ (Figure 1) 5.0 13.5 4.5 15.0
tPLH Propagation Delay, Clock to QA thru QH (Figure 1) 5.0 12.5 4.5 13.5
tPHL Propagation Delay, Clock to QA thru QH (Figure 1) 6.0 15.0 5.0 16.5
tPZH Propagation Delay , OE1, OE2 to QA thru QH
(Figure 3)
3.5 11.0 3.0 12.5
tPZL Propagation Delay , OE1, OE2 to QA thru QH
(Figure 3)
3.5 11.5 3.0 13.0
tPHZ Propagation Delay , OE1, OE2 to QA thru QH
(Figure 3)
4.0 12.5 3.0 13.5
tPLZ Propagation Delay , OE1, OE2 to QA thru QH
(Figure 3)
3.0 11.5 2.5 12.5
CIN Maximum Input Capacitance
4.5
4.5
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
pF
CPD Power Dissipation Capacitance
Typical @25°C,VCC=5.0 V
170
pF
TIMING REQUIREMENTS(VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=3.0 ns)
Symbol
Parameter
tsu Minimum Setup Time, Mode Select S1 or S2 to Clock (Figure 4)
tsu Minimum Setup Time, Data Inputs PA thru PH to Clock (Figure 4)
tsu Minimum Setup Time, Data Inputs SA, SH to Clock (Figure 4)
tsu Minimum Setup Time, Reset to Clock (Figure 2)
th Minimum Hold Time, Clock to Mode Select S1 or S2 (Figure 4)
th Minimum Hold Time, Clock to Data Inputs PA thru PH (Figure 4)
th Minimum Hold Time, Clock to Data Inputs SA, SH (Figure 4)
th Minimum Hold Time, Clock to Reset (Figure 2)
tw Minimum Pulse Width, Clock (Figure 1)
Guaranteed Limits
25 °C -40°C to Unit
85°C
5.0
5.0
ns
4.0
4.5
ns
4.5
5.0
ns
2.5
2.5
ns
1.5
1.5
ns
1.0
1.0
ns
1.0
1.0
ns
1.0
1.0
ns
4.0
4.5
ns
Rev. 00
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