IN7472 데이터 시트보기 (PDF) - Integral Corp.

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IN7472

AND-Gated J-K Master-Slave Flip-Flops with Reset and Clear

Integral Corp. 

AND-Gated J-K Master-Slave Flip-

Flops with Reset and Clear

LOGIC DIAGRAM

TECHNICAL DATA

IN7472

ORDERING INFORMATION

IN7472N Plastic

IN7472D SOIC

TA = -10° to 70° C for all packages

PIN ASSIGNMENT

PIN 14 =VCC

PIN 7 = GND

FUNCTION TABLE

NC - No internal connection

Inputs

Output

Reset Clear Clock J K Q Q

L

H

X XXH L

H

L

X XX L H

L

L

X

X X H* H*

H

H

L L Q0 Q0

H

H

HLH L

H

H

LHL H

H

H

H H TOGGLE

X =don’t care

Q0 = the level of Q before the indicated input conditions were established.

TOGGLE: Each output changes to the complement of its previous level on each

active transition (pulse) of the clock.

*This configuration is nonstable; that is, it will not persist whenpreset and clear inputs

return to their inactive (high) level.

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