SL70D0948 데이터 시트보기 (PDF) - System Logic Semiconductor

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SL70D0948

48 OUTPUT LED DRIVER / 9 BIT PWM CONTROLLER

System Logic Semiconductor 

SLS System Logic Semiconductor

SL70D0948

PIN DESCRIPTION

PIN No.

(MQFP)

PIN NAME

FUNCTION

49,52,53,54,78,99

9, 16, 23, 33,

34, 41, 48,

59, 65, 72,74

84, 91, 98

83

VDD

GND

/R E S E T

5V Power supply terminal.

GND terminals for LED Drivers and control logic.

All GND terminals must be connected to GND level.

Do not left any GND terminal to NC.

Reset input terminal (Low active).

100, 1, 2,

3, 4, 5,

6, 7, 8

32, 31, 30,

29, 28, 27,

26, 25, 24

DIN8 ~ DIN0

Data input terminals for 9bit R, G, B data.

Shift register accepts R, G, B data from these terminals.

(at rising edge of SHCLK)

DOUT8 ~ DOUT0

Output terminals of shift register output data for next

DIN8 ~ DIN0 terminals.

82

SHCLK

Shift register clock input terminal.

Strobe signal input terminal. At rising edge of strobe signal,

81

STROBE

48 channels of 9 bit data registers copy R, G, B data from

shift register.

80

/C E 1

Chip enable signal input terminal (Low active).

Chip enable signal input terminal (High active).

79

CE2

T h e d e v i c e a c c e p t s S H C L K a n d S T R O B E w h e n / C E 1 = “L ”

a n d C E 2 = “H ”.

Output enable signal input terminal.

76

OEB

T h e d e v i c e o u t p u t s d a t a w h e n O E B = “L ”. W h e n O E B = “H ”

all R, G, B output terminals hold high-impedance state.

77

PWCLK

PWM generator reference clock input terminal.

75

BRMODE

Brightness control mode input terminal.

56, 57, 58

BRD2 ~ BRD0

Brightness control data input terminal.

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