IDT7M1024S20G 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT7M1024S20G Datasheet PDF : 8 Pages
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IDT7M1024
4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1, 2 and 3
2909 tbl 10
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA OUT
Zo = 50Ω
Figure 1. Output Load
50Ω
1.5V
2809 drw 03
DATA OUT
775Ω
5V
1250Ω
5pF*
2809 drw 04
Figure 2. Output Load (for tCLZ, tCHZ, tOLZ, and tOHZ)
*Including scope and jig.
8
7
6
∆TAA
(Typical, ns)
5
4
3
2
1
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
2809 drw 05
Figure 3. Lumped Capacitive Load, Typical Derating
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE RANGE —
(READ AND WRITE CYCLE TIMING)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
7M1024SxxG, 7M1024SxxGB
–20
–25
–30
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
tCLK Clock Cycle Time
20 —
25 — 30 — ns
tCLKH Clock HIGH Time
8—
10 — 12 — ns
tCLKL Clock LOW Time
8—
10 — 12 — ns
tCQV Clock HIGH to Output Valid
— 20
— 25 — 30 ns
tRSU Registered Signal Set-up Time
5—
6 — 7 — ns
tRHD Registered Signal Hold Time
2—
2 — 2 — ns
tCOH Data Output Hold After Clock HIGH
3—
3 — 3 — ns
tCLZ Clock HIGH to Output Low-Z
2—
2 — 2 — ns
tCHZ Clock HIGH to Output High-Z
29
2 12 2 15 ns
tOE
Output Enable to Output Valid
— 10
— 12 — 15 ns
tOLZ Output Enable to Output Low-Z
0—
0 — 0 — ns
tOHZ Output Disable to Output High-Z
—9
— 11 — 14 ns
tCSU Clock Enable, Disable Set-up Time
5—
6 — 7 — ns
tCHD Clock Enable, Disable Hold Time
3—
3 — 3 — ns
Port-to-Port Delay
tCWDD Write Port Clock HIGH to Read Data Delay
— 35
— 45 — 55 ns
2809 tbl 11
7.4
5
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