IDT74SSTUBF32865A 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT74SSTUBF32865A Datasheet PDF : 17 Pages
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IDT74SSTUBF32865A
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
COMMERCIAL TEMPERATURE GRADE
Parity and Standby Function Table
RESET DCS0 DCS1 CLK
Inputs1
CLK Σ of Inputs = H (D1 - D21)
PARIN2
Outputs
PTYERR3
H
L
X
↑
↓
Even
L
H
H
L
X
↑
↓
Odd
L
L
H
L
X
↑
↓
Even
H
L
H
L
X
↑
↓
Odd
H
H
H
X
L
↑
↓
Even
L
H
H
X
L
↑
↓
Odd
L
L
H
X
L
↑
↓
Even
H
L
H
X
L
↑
↓
Odd
H
H
H
H
H
↑
↓
H
X
X
L or H L or H
L
X or
X or
X or
X or
Floating Floating Floating Floating
X
X
X or Floating
X
X
X or Floating
PTYERR0
PTYERR0
H
1 H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
2 PARIN arrives one clock cycle after the data to which it applies.
3 This transition assumes PTYERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If
PTYERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW.
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
6
IDT74SSTUBF32865A 7092/10
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