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IDT54FCT621ATD

FAST CMOS OCTAL BUS TRANSCEIVER (OPEN DRAIN)

Integrated Device Technology 

IDT54/74FCT621T/AT

FAST CMOS OCTAL BUS TRANSCEIVER (OPEN DRAIN)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS

TEST CIRCUITS FOR ALL OUTPUTS

V CC

7.0V

VIN

Pulse

Generator

D.U.T.

RT

VOUT

50pF

CL

500Ω

500Ω

SWITCH POSITION

Test

Switch

Open Drain

Disable Low

Closed

Enable Low

All Other Tests

Open

DEFINITIONS:

2538 lnk 08

CL= Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

2538 drw 03

SET-UP, HOLD AND RELEASE TIMES

PULSE WIDTH

DATA

INPUT

TIMING

tSU

tH

3V

1.5V

0V

3V

LOW-HIGH-LOW

PULSE

INPUT

1.5V

ASYNCHRONOUS CONTROL

PRESET

tREM

0V

3V

tW

CLEAR

ETC.

1.5V

0V

HIGH-LOW-HIGH

PULSE

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

tSU

tH

3V

1.5V

0V

ETC.

2538 drw 04

1.5V

1.5V

2538 drw 05

PROPAGATION DELAY

SAME PHASE

INPUT TRANSITION

tPLH

tPHL

OUTPUT

tPLH

tPHL

OPPOSITE PHASE

INPUT TRANSITION

ENABLE AND DISABLE TIMES

3V

1.5V

0V

VOH

1.5V

VOL

3V

1.5V

0V

2538 drw 06

ENABLE

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

tPZL

SWITCH

CLOSED

tPZH

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

DISABLE

tPLZ

3.5V

1.5V

0.3V

tPHZ

1.5V

0V

0.3V

3V

1.5V

0V

3.5V

VOL

VOH

0V

2538 drw 07

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-

HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns

6.18

5

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