IDT72V3612(2014) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72V3612
(Rev.:2014)

3.3 VOLT CMOS SyncBiFIFO 64 x 36 x 2

Integrated Device Technology 

IDT72V3612 3.3V, CMOS SyncBiFIFOTM

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF

SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

Commercial: Vcc=3.3V± 0.30V; for 12ns (83MHz) operation, Vcc=3.3V ±0.15V; TA = 0° C to +70°C; JEDEC JESD8-A compliant

Symbol

fS

tCLK

tCLKH

tCLKL

tDS

tENS1

tENS2

tENS3

tPGS

tRSTS

tFSS

tDH

tENH1

tENH2

tENH3

tPGH

tRSTH

tFSH

tSKEW1(3)

tSKEW2(3,4)

Parameter

Clock Frequency, CLKA or CLKB

Clock Cycle Time, CLKA or CLKB

Pulse Duration, CLKA and CLKB HIGH

Pulse Duration, CLKA and CLKB LOW

Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑

Setup Time, CSA, W/RA before CLKA↑; CSB, W/RB before CLKB↑

Setup Time, ENA, before CLKA↑; ENB before CLKB↑

Setup Time, MBA before CLKA↑: MBB before CLKB↑

Setup Time, ODD/EVEN and PGA before CLKA↑;

ODD/EVEN and PGB before CLKB↑(1)

Setup Time, RST LOW before CLKA↑ or CLKB↑(2)

Setup Time, FS0/FS1 before RST HIGH

Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑

Hold Time, CSA W/RA after CLKA↑; CSB, W/RB after CLKB↑

Hold Time, ENA, after CLKA↑; ENB after CLKB↑

Hold Time, MBA after CLKA↑; MBB after CLKB↑

Hold Time, ODD/EVEN and PGA after CLKA↑;

ODD/EVEN and PGB after CLKB↑(1)

Hold Time, RST LOW after CLKA↑ or CLKB↑(2)

Hold Time, FS0 and FS1 after RST HIGH

Skew Time, between CLKA↑ and CLKB↑ for EFA, EFB,

FFA, and FFB

Skew Time, between CLKA↑ and CLKB↑ for AEA, AEB,

AFA, and AFB

IDT72V3612L12 IDT72V3612L15

Min.

Max.

Min.

Max.

Unit

–

83

–

66.7

MHz

12

–

15

–

ns

5

–

6

–

ns

5

–

6

–

ns

4

–

4

–

ns

3.5

–

6

–

ns

3.5

–

4

–

ns

3.5

–

4

–

ns

3

–

4

–

ns

4

–

5

–

ns

4

–

5

–

ns

0.5

–

1

–

ns

0.5

–

1

–

ns

1

–

1

–

ns

1

–

1

–

ns

0

–

1

–

ns

4

–

5

–

ns

4

–

4

–

ns

5.5

–

8

–

ns

14

–

14

–

ns

NOTES:

1. Only applies for a clock edge that does a FIFO read.

2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

4. Design simulated, not tested.

7

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