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IDT72805LB
Integrated Device Technology
IDT72805LB Datasheet PDF : 26 Pages
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IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
Each of the two FIFOs contained in a single IDT72805LB/72815LB/
72825LB/72845LB may be used as a stand-alone device when the application
requirements are for 256/512/1,024/4,096 words or less. These FIFOs are in
a single Device Configuration when the First Load (FL), Write Expansion In
(WXI) and Read Expansion In (RXI) control inputs are configured as (FL, RXI,
WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset (Figure
28).
RESET (RS)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
DATA IN (D0 - D17)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE (PAE)
HALF-FULL FLAG (HF)
IDT
72805
72815
72825
72845
FIFO A OR B
FL
RXI WXI
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
DATA OUT (Q0 - Q17)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE (PAF)
3139 drw 28
Figure 28. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 Synchronous FIFO
(One of the two FIFOs contained in the IDT72805LB/72815LB/72825LB/72845LB)
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of FIFO A and B. Status flags can be detected from any one device.
The exceptions are the Empty Flag/Output Ready and Full Flag/Input
Ready. Because of variations in skew between RCLK and WCLK, it is
possible for flag assertion and deassertion to vary by one cycle between
FIFOs. To avoid problems the user must create composite flags by gating
the Empty Flags/Output Ready of every FIFO, and separately gating all Full
Flags/Input Ready. Figure 29 demonstrates a 36-word width by using one
IDT72805LB/72815LB/72825LB/72845LBs. Any word width can be attained
by adding additional IDT72805LB/72815LB/72825LB/72845LBs. These FIFOs
are in a single Device Configuration when the First Load (FL), Write Expansion
In (WXI) and Read Expansion In (RXI) control inputs are configured as (FL,
RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset
(Figure 29). Please see the Application Note AN-83.
RESET (RS)
RESET (RS)
DATA IN (D) 36
18
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
PROGRAMMABLE (PAE)
HALF FULL FLAG (HF)
FIFO A
18
FIFO B
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAF)
EMPTY FLAG/OUTPUT
READY (EF/OR)
FULL FLAG/INPUT
READY (FF/IR)
FF/IR
EF/OR
FL WXI RXI
18
FF/IR
EF/OR
FL WXI RXI
18 DATA OUT (Q) 36
NOTE:
1. Do not connect any output control signals directly together.
Figure 29. Block Diagram of the two FIFOs contained in one IDT72805LB/72815LB/72825LB/72845LB
configured for a 36-bit Width Expansion
3139 drw 29
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