IDT72805LB(1996) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72805LB
(Rev.:1996)

CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1024 x 18

Integrated Device Technology 

IDT72805/72815/72825 CMOS Dual SyncFIFO™

256 x 18-BIT, 512 x 18, and 1024 x 18

COMMERCIAL TEMPERATURE RANGE

FIRST LOAD (FLA, FLB)

First Load (FLA, FLB) is grounded to indicate operation in

the Single Device or Width Expansion mode. In the Depth

Expansion configuration, FL is grounded to indicate it is the

first deBvice loaded and is set to HIGH for all other devices in

the daisy chain. (See Operating Configurations for further

details.)

WRITE EXPANSION INPUT (WXIA, WXIB)

This is a dual purpose pin. Write Expansion In (WXIA,

WXIB) is grounded to indicate operation in the Single Device

or Width Expansion mode. WXI is connected to Write Expan-

sion Out (WXOA, WXOB) of the previous device in the Depth

Expansion or Daisy Chain mode.

READ EXPANSION INPUT (RXIA, RXIB)

This is a dual purpose pin. Read Expansion In (RXIA, RXIB)

is grounded to indicate operation in the Single Device or Width

Expansion mode. RXI is connected to Read Expansion Out

(RXOA, RXOB) of the previous device in the Depth Expansion

or Daisy Chain mode.

EMPTY FLAG (EFA, EFB)

The Empty Flag (EFA, EFB) will go LOW, inhibiting further

read operations, when the read pointer is equal to the write

pointer, indicating the device is empty.

The EF is updated on the LOW-to-HIGH transition of RCLK.

17

9

0

EMPTY OFFSET REGISTER

DEFAULT VALUE

001FH (72805) 003FH (72815):

007FH (72825)

17

9

0

FULL OFFSET REGISTER

DEFAULT VALUE

001FH (72805) 003FH (72815):

007FH (72825)

3139 drw 03

OUTPUTS:

FULL FLAG (FFA, FFB)

The Full Flag (FFA, FFB) will go LOW, inhibiting further write

operation, indicating that the device is full. If no reads are

performed after RS, FF will go LOW after 256 writes for the

IDT72805LB, 512 writes for the IDT72815LB, 1024 writes for

the IDT72825LB.

FF is updated on the LOW-to-HIGH transition of WCLK.

NOTE:

1. Any bits of the offset register not being programmed should be set to zero.

Figure 3. Offset Register Location and Default Values

TABLE I — STATUS FLAGS

Number of Words in FIFO

72805

72815

72825

0

0

0

1 to n(1)

1 to n(1)

1 to n(1)

(n + 1) to 128

(n + 1) to 256

(n + 1) to 512

129 to (256-(m+1))

257 to (512-(m+1))

513 to (1024-(m+1))

(256-m)(2) to 255

(512-m)(2) to 511

(1024-m)(2) to 1023

256

512

1024

NOTES:

1. n = Empty Offset (Default Values : 72805 n=31, 72815 n = 63, 72825 n = 127)

2. m = Full Offset (Default Values : 72805 n=31, 72815 n = 63, 722825 n = 127)

FFA PAFA HFA PAEA EFA

FFB PAFB HFB PAEB EFB

H

H

H

L

L

H

H

H

L

H

H

H

H

H

H

H

H

L

H

H

H

L

L

H

H

L

L

L

H

H

3139 tbl 09

PROGRAMMABLE ALMOST-FULL FLAG (PAFA, PAFB)

The Programmable Almost-Full Flag (PAFA, PAFB) will go

LOW when FIFO reaches the Almost-Full condition. If no

reads are performed after RS, the PAF will go LOW after (256-

m) writes for the IDT72805LB, (512-m) writes for the

IDT72815LB, (1024-m) writes for the IDT72825LB. The offset

“m” is defined in the FULL offset register.

If there is no Full offset specified, the PAF will be LOW when

the device is 31 away from completely full for 72805LB, 63

away from completely full for 72815LB, and 127 away from

completely full for 72825LB.

The PAF is asserted LOW on the LOW-to-HIGH transition

of the WCLK. PAF is reset to HIGH on the LOW-to-HIGH

transition of RCLK. Thus PAF is asychronous.

5.17

7

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