IDT72805LB(1996) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72805LB
(Rev.:1996)

CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1024 x 18

Integrated Device Technology 

IDT72805/72815/72825 CMOS Dual SyncFIFO™

256 x 18-BIT, 512 x 18, and 1024 x 18

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION

Symbol

DA0–DA17

DB0–DB17

RSA

RSB

WCLKA

WCLKB

WENA

WENB

RCLKA

RCLKB

RENA

RENB

OEA

OEB

LDA

LDB

FLA

FLB

WXIA

WXIB

RXIA

RXIB

EFA

EFB

PAEA

PAEB

PAFA

PAFB

FFA

FFB

WXOA/HFA

WXOB/HFB

RXOA

RXOB

QA0–QA17

QB0–QB17

VCC

GND

Name

Data Inputs

Reset

Write Clock

Write Enable

Read Clock

Read Enable

Output Enable

Load

First Load

Write Expansion

Input

Read Expansion

Input

Empty Flag

Programmable

Almost-Empty Flag

Programmable

Almost-Full Flag

Full Flag

Write Expansion

Out/Half-Full Flag

Read Expansion

Out

Data Outputs

Power

Ground

I/O Description

I Data inputs for a 18-bit bus.

I When RS is set LOW, internal read and write pointers are set to the first location of the

RAM array, FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before

an initial WRITE after power-up.

I When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK,

if the FIFO is not full.

I When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of

WCLK. When WEN is HIGH, the FIFO holds the previous data. Data will not be written

into the FIFO if the FF is LOW.

I When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if

the FIFO is not empty.

I When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of

RCLK. When REN is HIGH, the output register holds the previous data. Data will not be

read from the FIFO if the EF is LOW.

I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will

be in a high-impedance state.

I When LD is LOW, data on the inputs D0–D9 is written to the offset and depth registers

on the LOW-to-HIGH transition of the WCLK, when WEN is LOW. When LD is LOW,

data on the outputs Q0–Q9 is read from the offset and depth registers on the LOW-to-

HIGH transition of the RCLK, when REN is LOW.

I In the single device or width expansion configuration, FL is grounded. In the depth

expansion configuration, FL is grounded on the first device (first load device) and set to

HIGH for all other devices in the daisy chain.

I In the single device or width expansion configuration, WXI is grounded. In the depth

expansion configuration, WXI is connected to WXO (Write Expansion Out) of the

previous device.

I In the single device or width expansion configuration, RXI is grounded. In the depth

expansion configuration, RXI is connected to RXO (Read Expansion Out) of the previous

device.

O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited.

When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK.

O When PAE is LOW, the FIFO is almost empty based on the offset programmed into the

FIFO. The default offset at reset is 31 from empty for 72805LB, 63 from empty for

72815LB, and 127 from empty for 72825LB.

O When PAF is LOW, the FIFO is almost full based on the offset programmed into the FIFO.

The default offset at reset is 31 from full for 72805LB, 63 from full for 72815LB, and

127 from full for 72825LB.

O When FF is LOW, the FIFO is full and further data writes into the input are inhibited.

When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK.

O In the single device or width expansion configuration, the device is more than half full

when HF is LOW. In the depth expansion configuration, a pulse is sent from WXO to

WXI of the next device when the last location in the FIFO is written.

O In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device

when the last location in the FIFO is read.

O Data outputs for a 18-bit bus.

8 Vcc pins

9 GND pins

3139 tbl 01

5.17

3

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