IDT72805LB(1996) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72805LB
(Rev.:1996)

CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1024 x 18

Integrated Device Technology 

IDT72805/72815/72825 CMOS Dual SyncFIFO™

256 x 18-BIT, 512 x 18, and 1024 x 18

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)

Symbol Parameter

fS

tA

tCLK

tCLKH

tCLKL

tDS

tDH

tENS

tENH

tRS

tRSS

tRSR

tRSF

tOLZ

tOE

tOHZ

tWFF

tREF

tPAF

tPAE

tHF

tXO

tXI

tXIS

tSKEW1

tSKEW2

Clock Cycle Frequency

Data Access Time

Clock Cycle Time

Clock HIGH Time

Clock LOW Time

Data Set-up Time

Data Hold Time

Enable Set-up Time

Enable Hold Time

Reset Pulse Width(1)

Reset Set-up Time

Reset Recovery Time

Reset to Flag and Output Time

Output Enable to Output in Low-Z(2)

Output Enable to Output Valid

Output Enable to Output in High-Z(2)

Write Clock to Full Flag

Read Clock to Empty Flag

Clock to Programmable Almost-Full Flag

Clock to Programmable Almost-Empty Flag

Clock to Half-Full Flag

Clock to Expansion Out

Expansion In Pulse Width

Expansion In Set-Up Time

Skew time between Read Clock & Write Clock for

Full Flag

Skew time between Read Clock & Write Clock for

Empty Flag

NOTES:

1. Pulse widths less than minimum values are not allowed.

2. Values guaranteed by design, not currently tested.

COMMERCIAL TEMPERATURE RANGE

72805LB20

72815LB20

72825LB20

Min. Max.

—

50

2

12

20

—

8

—

8

—

5

—

1

—

5

—

1

—

20

—

12

—

12

—

—

35

0

—

—

9

1

9

—

12

—

12

—

30

—

30

—

30

—

12

8

—

8

—

14

—

Commercial

72805LB25

72815LB25

72825LB25

Min. Max.

—

40

3

15

25

—

10

—

10

—

6

—

1

—

6

—

1

—

25

—

15

—

15

—

—

40

0

—

—

12

1

12

—

15

—

15

—

35

—

35

—

35

—

15

10

—

10

—

16

—

72805LB35

72815LB35

72825LB35

Min. Max.

— 28.6

3

20

35

—

14

—

14

—

7

—

2

—

7

—

2

—

35

—

20

—

20

—

—

45

0

—

—

15

1

15

—

20

—

20

—

40

—

40

—

40

—

20

14

—

15

—

18

—

Unit

MHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

14

—

16

—

18

—

ns

3139 tbl 06

5V

AC TEST CONDITIONS

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

1.1K

GND to 3.0V

3ns

1.5V

1.5V

See Figure 1

3139 tbl 07

D.U.T.

680Ω

30pF*

3139 drw 05

Figure 1. Output Load

* Includes jig and scope capacitances.

5.17

5

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