IDT72805LB(1996) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72805LB
(Rev.:1996)

CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1024 x 18

Integrated Device Technology 

IDT72805/72815/72825 CMOS Dual SyncFIFO™

256 x 18-BIT, 512 x 18, and 1024 x 18

WCLK

tDS

D0 - D17

tENS

WEN

RCLK

DATA WRITE 1

tENH

tSKEW2

tFRL (1)

EF

tDS

tENS

tREF

COMMERCIAL TEMPERATURE RANGE

DATA WRITE 2

tENH

tSKEW2

(1)

tFRL

tREF

REN

OE

LOW

tA

Q0 - Q17

DATA IN OUTPUT REGISTER

DATA READ

3139 drw 09

NOTE:

1. When tSKEW2 ≥ minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2 * tCLK + tSKEW2.

or tCLK + tSKEW2. The Latency Timing apply only at the Empty Boundary (EF = LOW).

Figure 9. Empty Flag Timing

5.17

13

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