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IDT72205LB10TF(2000) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72205LB10TF
(Rev.:2000)
IDT
Integrated Device Technology IDT
IDT72205LB10TF Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
Symbol
Parameter
Commercial
Com'l & Ind'l(1)
72205LB10
72215LB10
72225LB10
72235LB10
72205LB15
72215LB15
72225LB15
72235LB15
72205LB25
72215LB25
72225LB25
72235LB25
72245LB10 72245LB15 72245LB25
Min. Max. Min. Max. Min. Max. Unit
fS
Clock Cycle Frequency
— 100 — 66.7 — 40 MHz
tA
Data Access Time
2
6.5
2
10 2
15 ns
tCLK Clock Cycle Time
10 — 15 — 25 — ns
tCLKH Clock HIGH Time
4.5 —
6
— 10 — ns
tCLKL Clock LOW Time
4.5 —
6
— 10 — ns
tDS
Data Set-up Time
3
4
—6
— ns
tDH
Data Hold Time
0
1
—1
ns
tENS Enable Set-up Time
3
4
—6
— ns
tENH Enable Hold Time
tRS
Reset Pulse Width(2)
0
1
—1
— ns
10 — 15 — 25 — ns
tRSS Reset Set-up Time
8
— 10 — 15 — ns
tRSR Reset Recovery Time
8
— 10 — 15 — ns
tRSF Reset to Flag and Output Time
— 15 — 20 — 25 ns
tOLZ Output Enable to Output in Low-Z(3)
0
0
—0
— ns
tOE
Output Enable to Output Valid
3
6
3
8
3
12 ns
tOHZ Output Enable to Output in High-Z(3)
3
6
3
8
3
12 ns
tWFF Write Clock to Full Flag
— 6.5 — 10 — 15 ns
tREF Read Clock to Empty Flag
— 6.5 — 10 — 15 ns
tPAF Clock to Programmable Almost-Full
Flag
— 17 — 24 — 26 ns
tPAE Clock to Programmable Almost-Empty — 17 — 24 — 26 ns
Flag
tHF
Clock to Half-Full Flag
— 17 — 24 — 26 ns
tXO
Clock to Expansion Out
— 6.5 — 10 — 15 ns
tXI
Expansion In Pulse Width
3
— 6.5 — 10 — ns
tXIS Expansion In Set-Up Time
3.5 —
5
— 10 — ns
tSKEW1 Skew time between Read Clock &
Write Clock for Full Flag
5
6
— 10 — ns
tSKEW2 Skew time between Read Clock &
Write Clock for Empty Flag
5
6
— 10 — ns
NOTES:
1. Industrial temperature range is available as standard product for the 15ns
and the 25ns speed grade.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
2766 tbl 07
5V
D.U.T.
680
1.1K
30pF*
2766 drw 04
Figure 1. Output Load
* Includes jig and scope capacitances.
5

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