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전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크

IDT7133LA45F 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT7133LA45F
IDT
Integrated Device Technology IDT
IDT7133LA45F Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(5)
tRC
ADDRESS
tAA
DATAOUT
tOH
PREVIOUS DATA VALID
tOH
DATA VALID
BUSYOUT
tBDD(3,4)
2746 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(5)
tACE(4)
CE
tAOE(4)
tHZ (2)
OE
tLZ (1)
tHZ (2)
DATAOUT
ICC
CURRENT
ISB
tLZ (1)
tPU
50%
VALID DATA
tPD
50%
2746 drw 08
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is deasserted first, OE or CE.
3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has no
relationship to valid output data.
4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD.
5. R/W = VIH, and the address is valid prior to or coincidental with CE transition LOW.
6.842

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