IDT7024S15PFGI(2018) 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT7024S15PFGI Datasheet PDF : 22 Pages
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IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
7024X15
Com'l Only
7024X17
Com'l Only
7024X20
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address Match
____
15
____
17
____
20
tBDA
BUSY Disable Time from Address Not Match
____
15
____
17
____
20
tBAC
BUSY Access Time from Chip Enable Low
____
15
____
17
____
20
tBDC
BUSY Disable Time from Chip Enable High
____
15
____
17
____
17
tAPS
Arbitration Priority Set-up Time(2)
5
____
5
____
5
____
tBDD
BUSY Disable to Valid Data(3)
____
18
____
18
____
30
tWH
Write Hold After BUSY(5)
12
____
13
____
15
____
BUSY INPUT TIMING (M/S = VIH)
tWB
BUSY Input to Write(4)
0
____
0
____
0
____
tWH
Write Hold After BUSY(5)
12
____
13
____
15
____
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
____
30
____
30
____
45
tDDD
Write Data Valid to Read Data Delay(1)
____
25
____
25
____
35
7024X25
Com'l &
Military
Min.
Max. Unit
____
20
ns
____
20
ns
____
20
ns
____
17
ns
5
____
ns
____
30
ns
17
____
ns
0
____
ns
17
____
ns
____
50
ns
____
35
ns
2740 tbl 14a
7024X35
Com'l &
Military
7024X55
Com'l, Ind
& Military
7024X70
Military Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address Match
____
20
____
45
____
45
ns
tBDA
BUSY Disable Time from Address Not Match
____
20
____
40
____
40
ns
tBAC
BUSY Access Time from Chip Enable Low
____
20
____
40
____
40
ns
tBDC
BUSY Disable Time from Chip Enable High
____
20
____
35
____
35
ns
tAPS
Arbitration Priority Set-up Time(2)
5
____
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
35
____
40
____
45
ns
tWH
Write Hold After BUSY(5)
25
____
25
____
25
____
ns
BUSY INPUT TIMING (M/S = VIH)
tWB
BUSY Input to Write(4)
0
____
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
25
____
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
____
60
____
80
____
95
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
45
____
65
____
80
ns
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port 'B' during contention with port 'A'.
5. To ensure that a write cycle is completed on port 'B' after contention with port 'A'.
6. 'X' in part number indicates power rating (S or L).
2740 tbl 14b
61.432
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