ICSSSTUB32864A 데이터 시트보기 (PDF) - Integrated Device Technology
부품명
상세내역
일치하는 목록
ICSSSTUB32864A Datasheet PDF : 12 Pages
| |||
ICSSSTUB32864A
Advance Information
Ball Assignment
Terminal Name
GND
VDD
VREF
ZOH
ZOL
CK
CK#
C0, C1
RST#
CSR#, DCS#
D1 - D25
DODT
DCKE
Q1 - Q25
QCS#
QODT
QCKE
Description
Electrical
Characteristics
Ground
Ground input
Power supply voltage
1.8V nominal
Input reference voltage
0.9V nominal
Reserved for future use
Input
Reserved for future use
Input
Positive master clock input
Differential input
Negative master clock input
Differential input
Configuration control inputs
LVCMOS inputs
Asynchronous reset input - resets registers and disables VREF data and
clock differential-input receivers
LVCMOS input
Chip select inputs - disables D1 - D24 outputs switching when both inputs
are high
SSTL_18 input
Data input - clock in on the crossing of the rising edge of CK and the
falling edge of CK#
SSTL_18 input
The outputs of this register bit will not be suspended by the DCS# and
CSR# control
SSTL_18 input
The outputs of this register bit will now be suspended by the DCS# and
CSR# control
SSTL_18 input
Data ouputs that are suspended by the DCS# and CSR# control
1.8V CMOS
Data output that will not be suspended by the DCS# and CSR# control 1.8V CMOS
Data output that will not be suspended by the DCS# and CSR# control 1.8V CMOS
Data output that will not be suspended by the DCS# and CSR# control 1.8V CMOS
1166—10/05/05
3
Share Link: 