ICSSSTV16857 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICSSSTV16857

DDR 14-Bit Registered Buffer

Integrated Circuit Systems 

ICSSSTV16857

General Description

The 14-bit ICSSTV16857 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels

except for the RESET# input which is LVCMOS.

Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the

positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supported with LVCMOS

levels as VREF may not be stable during power-up. RESET# is asynchronous and is intended for power-up only and

when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and

clock are switched off.

Pin Configuration

PIN NUMBER

24, 23, 20, 19, 18,

15, 14, 11, 10, 7, 6,

5, 2, 1

3, 8, 13, 22,

27, 36, 46

4, 9, 12, 16, 21

25, 26, 29, 30, 31,

32, 33, 40, 41, 42,

43, 44, 47, 48

38

39

28, 37, 45

34

35

PIN NAME

Q (14:1)

GND

VDDQ

D (14:1)

CLK

CLK#

VDD

RESET#

VREF

TYPE

OUTPUT

Data output

DESCRIPTION

PWR

PWR

INPUT

INPUT

INPUT

PWR

INPUT

INPUT

Ground

Output supply voltage

Data input

Positive clock input

Negative clock input

Core supply voltage

Reset (active low)

Input reference voltage

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