ICS9250-32 데이터 시트보기 (PDF) - Integrated Circuit Systems
부품명
상세내역
일치하는 목록
ICS9250-32 Datasheet PDF : 11 Pages
| |||
ICS9250-32
Byte 0: Active/Inactive Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
1
2
-
PWD
DESCRIPTION
0 Reserved
0 Reserved
0 Reserved
0 Reserved
0
Spread Spectrum
(0=On/1=Off
1 2V48M (DOT)
1 3V48M (USB)
1 Reserved
Byte 1: Active/Inactive Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
30
31
34
35
38
39
40
43
PWD
DESCRIPTION
1 SDRAM7
1 SDRAM6
1 SDRAM5
1 SDRAM4
1 SDRAM3
1 SDRAM2
1 SDRAM1
1 SDRAM0
Byte 2: Active/Inactive Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
22
21
18
17
16
15
12
11
PWD
DESCRIPTION
1 PCICLK7
1 PCICLK6
1 PCICLK5
1 PCICLK4
1 PCICLK3
1 PCICLK2
1 PCICLK1
1 PCICLK0
Byte 4: Active/Inactive Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7 -
0 Reserved
Bit 6 -
0 Reserved
Bit 5 -
0 Reserved
Bit 4 -
0 Reserved
Bit 3 -
0 Reserved
Bit 2 -
Bit 1 -
Bit 0 -
0 Reserved
0 Reserved
0 Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Byte 3: Active/Inactive Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
0
<>
<>
<>
0
0
0
0
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note:
<>, with these 3 bits, the registers will store the written
values. The read back, however, will be the invert of the
written value.
Third party brands and names are the property of their respective owners.
4
Share Link: 