ICS9250-25 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICS9250-25 Datasheet PDF : 14 Pages
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ICS9250-25
Preliminary Product Preview
Byte 0: Functionality and frequency select register (Default=0)
(1 = enable, 0 = disable)
Bit
Description
Bit
(2, 7:4)
Bit 3
Bit 1
Bit 0
Bit (2,7:4)
CPUCLK SDRAM
MHz
MHz
0 0 0 0 0 55.00
82.50
0 0 0 0 1 60.00
90.00
0 0 0 1 0 66.80
100.20
0 0 0 1 1 68.33
102.50
0 0 1 0 0 70.00
105.00
0 0 1 0 1 72.00
108.00
0 0 1 1 0 75.00
112.50
0 0 1 1 1 77.00
115.50
0 1 0 0 0 83.30
83.30
0 1 0 0 1 90.00
90.00
0 1 0 1 0 100.30
100.30
0 1 0 1 1 103.00
103.00
0 1 1 0 0 112.50
112.50
0 1 1 0 1 115.00
115.00
0 1 1 1 0 120.00
120.00
0 1 1 1 1 125.00
125.00
1 0 0 0 0 128.00
128.00
1 0 0 0 1 130.00
130.00
1 0 0 1 0 133.70
133.70
1 0 0 1 1 137.00
137.00
1 0 1 0 0 140.00
140.00
1 0 1 0 1 145.00
145.00
1 0 1 1 0 150.00
150.00
1 0 1 1 1 153.33
153.33
1 1 0 0 0 125.00
93.75
1 1 0 0 1 130.00
97.50
1 1 0 1 0 133.70
100.28
1 1 0 1 1 137.00
102.75
1 1 1 0 0 140.00
105.00
1 1 1 0 1 145.00
108.75
1 1 1 1 0 150.00
112.50
1 1 1 1 1 153.33
115.00
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,6:4
0- Normal
1- Spread spectrum enable ± 0.25% Center Spread
0- Running
1- Tristate all outputs
3V66
MHz
55.00
60.00
66.80
68.33
70.00
72.00
75.00
77.00
55.53
60.00
66.87
68.67
75.00
76.67
80.00
83.33
64.00
65.00
66.85
68.50
70.00
72.50
75.00
76.67
62.50
65.00
66.85
68.50
70.00
72.50
75.00
76.67
PCICLK
27.5
30
33.4
34.165
35
36
37.5
38.5
27.8
30.0
33.4
34.3
37.5
38.3
40.0
41.7
32.0
32.5
33.4
34.3
35.0
36.3
37.5
38.3
31.3
32.5
33.4
34.3
35.0
36.3
37.5
38.3
IOAPIC
MHz
13.75
15
16.7
17.0825
17.5
18
18.75
19.25
13.9
15.0
16.7
17.2
18.8
19.2
20.0
20.8
16.0
16.3
16.7
17.1
17.5
18.1
18.8
19.2
15.6
16.3
16.7
17.1
17.5
18.1
18.8
19.2
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
2. The I2C readback for Bit 2, 7:4 indicate the revision code.
Third party brands and names are the property of their respective owners.
4
PWD
00001
Note 1
0
1
0
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