ICS9250-18 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICS9250-18 Datasheet PDF : 15 Pages
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ICS9250-18
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit
2,7, 6:4
Bit 3
Bit 1
Bit 0
Description
Bit2 Bit7 Bit6 Bit5
Bit4
CPUCLK
MHz
PCICLK
MHz
0
0
0
0
0
80.00
40.00
0
0
0
0
1
75.00
37.50
0
0
0
1
0
83.31
41.65
0
0
0
1
1
66.9
33.45
0
0
1
0
0
103.00
34.33
0
0
1
0
1
112.01
37.34
0
0
1
1
0
68.01
34.01
0
0
1
1
1
100.7
33.57
0
1
0
0
0
120.00
40.00
0
1
0
0
1
114.99
38.33
0
1
0
1
0
109.99
36.66
0
1
0
1
1
105.00
35.00
0
1
1
0
0
140.00
35.00
0
1
1
0
1
150.00
37.50
0
1
1
1
0
124.00
31.00
0
1
1
1
1
133.9
33.25
1
0
0
0
0
135.00
33.75
1
0
0
0
1
129.99
32.50
1
0
0
1
0
126.00
31.50
1
0
0
1
1
118.00
39.33
1
0
1
0
0
115.98
38.66
1
0
1
0
1
95.00
31.67
1
0
1
1
0
90.00
30.00
1
0
1
1
1
85.01
28.34
1
1
0
0
0
166.00
41.50
1
1
0
0
1
160.01
40.00
1
1
0
1
0
154.99
38.75
1
1
0
1
1
147.95
36.99
1
1
1
0
0
145.98
36.50
1
1
1
0
1
143.98
35.99
1
1
1
1
0
141.99
35.50
1
1
1
1
1
138.01
34.50
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2, 7:4
0 - Normal
1 - Spread Spectrum Enabled ±0.25% (Center Spread)
0 - Running
1- Tristate all outputs
Note 1. Default at Power-up will be for latched logic inputs to define frequency as
displayed by Bit 3.
Note: PWD = Power-Up Default
PWD
XXXX
Note1
0
1
0
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