ICS9250-10 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICS9250-10

Frequency Timing Generator for Pentium II Systems

Integrated Circuit Systems 

ICS9250 - 10

Preliminary Product Preview

Functionality Table

FS1 FS0

CPU

SDRAM

0

0

Hi-Z

Hi-Z

0

1

TCLK/2 TCLK/4

1

0

66 MHz 100 MHz

1

1

100 MHz 100 MHz

3V66

Hi-Z

TCLK/4

66 MHz

66 MHz

PCICLK

Hi-Z

TCLK/8

33 MHz

33MHz

48MHz

Hi-Z

TCLK/2

48 MHz

48 MHz

REF0

Hi-Z

TCLK

14.318MHz

14.318MHZ

IOAPIC

Hi-Z

TCLK/16

16.67MHz

16.67MHz

Notes

Tristate

Test Mode

Clock Enable Configuration

PD#

CPUCLK SDRAM

IOAPIC

66MHz

PCICLK

REF,

48MHz

Osc

0

LOW

LOW

LOW

LOW

LOW

LOW

OFF

1

ON

ON

ON

ON

ON

ON

ON

VCOs

OFF

ON

Select Functions

FS1 FS0

Notes

0

0 Tristate

0

1 Test Mode

1

0 Active CPU = 66MHz

1

1 Active CPU = 100MHz

3

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