ICS9250-30 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICS9250-30

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Integrated Circuit Systems 

Power Down Waveform

ICS9250-30

Preliminary Product Preview

Note

1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the

output clocks are driven Low on their next High to Low tranistiion.

2. Power-up latency <3ms.

3. Waveform shown for 100MHz

Third party brands and names are the property of their respective owners.

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