ICS9248-50(2003) 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICS9248-50
(Rev.:2003)

Frequency Timing Generator for Pentium II Systems

Integrated Circuit Systems 

PD# Timing Diagram

ICS9248-50

ICS9248-50

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).

2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.

3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.

0278I—06/03/03

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