ICS9248YF-138 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICS9248YF-138

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Integrated Circuit Systems 

ICS9248-138

Preliminary Product Preview

Absolute Maximum Ratings

Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V

Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are

stress specifications only and functional operation of the device at these or any other conditions above those listed in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect product reliability.

Group Timing Relationship Table

Group

CPU to SDRAM

CPU to 3V66

CPU 66MHz

SDRAM 100MHz

Offset Tolerance

2.5ns 500ps

7.5ns 500ps

CPU 100MHz

SDRAM 100MHz

Offset Tolerance

5.0ns 500ps

5.0ns 500ps

CPU 133MHz

SDRAM 100MHz

Offset Tolerance

0.0ns 500ps

0.0ns 500ps

CPU 133MHz

SDRAM 133MHz

Offset Tolerance

3.75ns 500ps

0.0ns 500ps

SDRAM to 3V66 0.0ns 500ps 0.0ns 500ps 0.0ns 500ps 3.75ns 500ps

3V66 to PCI

PCI to PCI

USB & DOT

1.5-3.5ns

0.0ns

Asynch

500ps

1.0ns

N/A

1.5-3.5ns

0.0ns

Asynch

500ps

1.0ns

N/A

1.5-3.5ns

0.0ns

Asynch

500ps

1.0ns

N/A

1.5 -3.5ns

0.0ns

Asynch

500ps

1.0ns

N/A

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Input High Voltage

Input Low Voltage

Input High Current

Input Low Current

Input Low Current

Operating

Supply Current

Power Down

Supply Current

VIH

VIL

IIH

IIL1

IIL2

IDD3.3OP

VIN = VDD

VIN = 0 V; Inputs with no pull-up resistors

VIN = 0 V; Inputs with pull-up resistors

CL = 0 pF; Select @ 66M

2

VSS-0.3

-5

-5

-200

IDD3.3PD CL = 0 pF; With input address to Vdd or GND

VDD+0.3 V

0.8

V

5

µA

µA

µA

100 mA

600 µA

Input frequency

Fi

VDD = 3.3 V;

Pin Inductance

Input Capacitance1

Lpin

CIN Logic Inputs

Cout Out put pin capacitance

Transition Time1

Settling Time1

Clk Stabilization1

CINX

Ttrans

Ts

TSTAB

X1 & X2 pins

To 1st crossing of target Freq.

From 1st crossing to 1% target Freq.

From VDD = 3.3 V to 1% target Freq.

Delay

tPZH,tPZH output enable delay (all outputs)

tPLZ,tPZH output disable delay (all outputs)

1Guarenteed by design, not 100% tested in production.

14.318

7

5

6

27

45

3

3

3

1

10

1

10

MHz

nH

pF

pF

pF

mS

mS

mS

nS

nS

Third party brands and names are the property of their respective owners.

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