ICS9214 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICS9214

Rambus™ XDR™ Clock Generator

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS9214

Revision History

Rev. Issue Date Description

Updated SMBus table Byte 2, Bit 3 from:0 to:1.

0.1 3/30/2005 Updated PLL Multiplier Selection Table, from: Byte 1 to: Byte 0, and Bit 2,1,0,

to: Bit 6,5,4.

Updated Ordering Information from "Lead Free" to "Annealed Lead Free"

Added Phase noise spec

Removed unsupported speeds from PLL Multiplier Selection,

Changed minimum output raise, fall times from 140ps to 100 ps

A

4/6/2005 Compliant with Rev 0.81 of XCG spec.

1. Changed write address from D2 to a valid address (D8)

B 4/22/2005 2. Changed read address from D3 to a valid address (D9)

C 11/11/2005 Added the 15/4 entry in the gear table to the list of supported frequencies

D

4/7/2006 Added Thermal Characteristics Table.

Page #

4-5,15

Various

3

5

10

0809D—04/07/06

16

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