ICS9147-06 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICS9147-06 Datasheet PDF : 6 Pages
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ICS9147-06
Functionality
PD#
BUSEN CPUEN
FS1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
X
1
0
1
X
0
X
X
X
FS0
CPU (1:4)
CPUH
BUS
REF
IOAPIC
24
(MHz)
48
(MHz)
0
Tristate Tristate Tristate Tristate Tristate
1
60
30
14.31818
24
48
0
66.6
33.3
14.31818
24
48
1
REF/2
REF/4
REF
REF/4
REF/2
X
LOW
Running 14.31818
24
48
X
Running
LOW
14.31818
24
48
X
LOW
LOW
LOW
LOW
LOW
Pin Descriptions
PIN NUMBER
1, 2, 47
3, 10, 18, 24, 30, 32,
37, 43, 44
PIN NAME
REF1, REF2, REF3
GND
4
X1
5
8, 9, 11, 12, 13, 14,
16, 17
26, 27
7, 15, 21, 25, 34, 48
22, 23
X2
BUS (1:8)
FS (0:1)
VDD3
48M (1:2)
28
PD#
29
36
38, 39, 41, 42
CPUEN
CPUH
CPU (1:4)
6
BUSEN
45
IOAPIC
40, 46
33
VDDL
24M
* Has internal pull-up to VDD3.
TYPE
DESCRIPTION
OUT 14.318 MHz reference clock outputs.
PWR Ground.
IN
OUT
Crystal input, has internal crystal load capacitor, and feedback resistor
from X2. Nominally 14.31818MHz.
Crystal output, has internal crystal load capacitor
OUT BUS clock outputs, operates synchronously at CPU/2.
IN
PWR
OUT
IN
IN
OUT
OUT
IN
OUT
PWR
OUT
Select pin for enabling CPU and BUS clock frequencies.*
Core and Buffer output clock power supply.
48 MHz clock output
Device power down input, stops outputs low and shuts off crystal
oscillator and PLLs when low.*
Output enable for all CPU clocks, a logic low will Stop low all CPU
clocks.*
3.3 (VDD3 dependent) CPU clock output
CPU clock output clocks, operates at VDDL supply voltage (with
IOAPIC), either nominal 3.3V VDD or reduced voltage 2.9 to 2.5V.
Output enable for all BUS clock, a logic low will stop Low all Bus
clocks.*
IOAPIC clock output. (14.318 MHz), operates at VDDL supply voltage
with CPU (1:4), either nominal 3.3V VDD or reduced voltage
2.9 to 2.5V.
Power supply for CPU and IOAPIC block buffers, operates at nominal
3.3V VDD or reduced voltage 2.9 to 2.5V.
24 MHz clock output
2
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