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ICS85211AMI

LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS85211I

LOW SKEW, 1-TO-2

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS85211I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS85211I is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.3mW

•

Power (outputs) = 78.88mW/Loaded Output pair

MAX

If all outputs are loaded, the total power is 2 * 78.88mW = 157.8mW

Total Power (3.465V, with all outputs switching) = 173.3mW + 157.8mW = 311.1mW

_MAX

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a

moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.311W * 103.3°C/W = 117.1°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

TABLE 6. THERMAL RESISTANCE qJA FOR 8-PIN SOIC, FORCED CONVECTION

qJA by Velocity (Linear Feet per Minute)

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

0

153.3°C/W

112.7°C/W

200

128.5°C/W

103.3°C/W

500

115.5°C/W

97.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

85211AMI

www.icst.com/products/hiperclocks.html

7

REV. B ARPIL 8, 2003

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