ICS810-06 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICS810-06

VCXO-TO-6 LVCMOS OUTPUTS

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS81006

VCXO-TO-6 LVCMOS OUTPUTS

TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum

fOUT

tjit(Ø)

Output Frequency

RMS Phase Jitter (Random);

NOTE 1

Integration Range: 1kHz- 1MHz

12

19.44

40

0.35

tsk(o)

Output Skew;

NOTE 2, 3

Q0:Q4

Q0:Q5

DIV_SEL_Q5 = ÷1

30

100

tR / tF

odc

Output Rise/Fall Time

Output Duty Cycle

20% to 80%

200

700

44

56

NOTE 1: Please refer to the Phase Noise Plot.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

Units

MHz

ps

ps

ps

ps

%

TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum

fOUT

tjit(Ø)

tsk(o)

Output Frequency

RMS Phase Jitter (Random);

NOTE 1

Output Skew;

NOTE 2, 3

Q0:Q4

Q0:Q5

Integration Range: 1kHz- 1MHz

DIV_SEL_Q5 = ÷1

12

19.44

40

0.38

20

90

tR / tF

odc

Output Rise/Fall Time

Output Duty Cycle

20% to 80%

300

800

45

55

NOTE 1: Please refer to the Phase Noise Plot.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

Units

MHz

ps

ps

ps

ps

%

TABLE 4C. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum

fOUT

tjit(Ø)

tsk(o)

Output Frequency

RMS Phase Jitter (Random);

NOTE 1

Output Skew;

NOTE 2, 3

Q0:Q4

Q0:Q5

Integration Range: 1kHz-1MHz

DIV_SEL_Q5 = ÷1

12

19.44

40

0.27

46

175

tR / tF

odc

Output Rise/Fall Time

Output Duty Cycle

20% to 80%

450

44

NOTE 1: Please refer to the Phase Noise Plot.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

1400

56

Units

MHz

ps

ps

ps

ps

%

81006AK

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4

REV. A JANUARY 4, 2006

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