ICS8312AYT 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICS8312AYT Datasheet PDF : 12 Pages
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Integrated
Circuit
Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 5, 8, 12,
16, 17, 21,
25, 29
GND
Power
Power supply ground.
2, 7
VDD
Power
Core supply pins.
3
CLK_EN
Input
Pullup
Synchronous control for enabling and disabling clock outputs.
LVCMOS / LVTTL interface levels.
4
CLK
Input Pulldown Clock input. LVCMOS / LVTTL interface levels.
6
OE
Input
Pullup
Output enable. Controls enabling and disabling of outputs
Q0 thru Q11. LVCMOS / LVTTL interface levels.
9, 11, 13, 15,
18, 20, 22,
24, 26, 28,
30, 32
Q11, Q10, Q9, Q8,
Q7, Q6, Q5,
Q4, Q3, Q2,
Q1, Q0
Output
Q0 thru Q11 outputs. LVCMOS / LVTTL interface levels.
10, 14, 19,
23, 27, 31
VDDO
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Input Capacitance
CPD
Power Dissipation Capacitance
(per output)
RPULLUP
RPULLDOWN
Input Pullup Resistor
Input Pulldown Resistor
R
OUT
Output Impedance
Test Conditions
VDDO = 3.465V
VDDO = 2.625V
VDDO = 2V
VDDO = 3.3V ± 5%
V = 2.5V ± 5%
DDO
VDDO = 1.8V ± 0.2V
Minimum
Typical
4
51
51
7
7
10
Maximum
19
18
16
Units
pF
pF
pF
pF
KΩ
KΩ
Ω
Ω
Ω
TABLE 3A. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE
Control Inputs
OE
CLK_EN
0
X
1
0
1
1
Output
Q0:Q11
Hi-Z
LOW
Follows CLK input
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
OE
CLK_EN
CLK
1
1
0
1
1
1
Outputs
Q0:Q11
LOW
HIGH
8312AY
http://www.icst.com/products/hiperclocks.html
2
REV. C JUNE 14, 2004
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