ICS670-03 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICS670-03 Datasheet PDF : 6 Pages
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ICS670-03
LOW PHASE NOISE, ZERO DELAY BUFFER AND MULTIPLIER
Figure 1. Skew from ICLK to CLK2, with change in load capacitance (VDD = 3.3V)
300
200
100
0
-100
25
-200
-300
-400
50
75
100
125
150
CLK2 Frequency (MHz)
Skew (ps) 20 pF
Skew (ps) 10 pF
Adjusting Input/Output Skew
The data in Figure 1 can be used to adjust individual circuit characteristics and achieve the minimum
possible skew between ICLK and CLK2. With a 125 MHz output, for example, having a total load
capacitance of 15 pF will result in nearly zero skew between ICLK and CLK2. Note that the load
capacitance includes board trace capacitance, input capacitance of the load being driven by the
ICS670-03, and any additional capacitors connected to CLK2.
Figure 2. Phase Noise at 125 MHz out, 25 MHz clock input (VDD = 3.3V)
ICS670 Phase noise
0
-20
-40
-60
-80
-100
-120
-140
10.E+0
100.E+0
1.E+3
10.E+3
offset frequency
100.E+3
1.E+6
10.E+6
MDS 670-03 G
5
Revision 010306
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
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