ICS650-41 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICS650-41

Spread Spectrum Clock Synthesizer

Integrated Circuit Systems 

ICS650-41

Spread Spectrum Clock Synthesizer

PCB Layout Recommendations

For optimum device performance and lowest output

phase noise, the following guidelines should be

observed.

1) The 0.01µF decoupling capacitors should be

mounted on the component side of the board as close

to the VDD pin as possible. No vias should be used

between the decoupling capacitors and VDD pins. The

PCB trace to VDD pins should be kept as short as

possible, as should the PCB trace to the ground via.

2) The external crystal should be mounted just next to

the device with short traces. The X1 and X2 traces

should not be routed next to each other with minimum

spaces, instead they should be separated and away

from other traces.

3) To minimize EMI, the 33Ω series termination resistor

(if needed) should be placed close to the clock output.

4) An optimum layout is one with all components on the

same side of the board, minimizing vias through other

signal layers. Other signal traces should be routed

away from the ICS650-41. This includes signal traces

just underneath the device, or on layers adjacent to the

ground plane layer used by the device.

MDS 650-41 F

4

Revision 082305

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

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