ICS570
Multiplier and Zero Delay Buffer
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
8
INDEX
AREA
12
D
e
B
EH
A
Symbol
A
A1
B
C
D
E
e
H
h
L
α
A1
-C-
SEATING
PLANE
C .10 (.004)
Millimeters
Min
Max
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BASIC
5.80
6.20
0.25
0.50
0.40
1.27
0°
8°
h x 45
Inches
Min
Max
.0532 .0688
.0040 .0098
.013
.020
.0075 .0098
.1890 .1968
.1497 .1574
0.050 BASIC
.2284 .2440
.010
.020
.016
.050
0°
8°
C
L
MDS 570 I
8
Revision 030905
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com