ICE2QS03G 데이터 시트보기 (PDF) - Infineon Technologies
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ICE2QS03G Datasheet PDF : 19 Pages
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Quasi-Resonant PWM Controller
ICE2QS03G
Functional Description
3.4.1
Foldback Point Correction
When the main bus voltage increases, the switch on
time becomes shorter and therefore the operating
frequency is also increased. As a result, for a constant
primary current limit, the maximum possible output
power is increased, which the converter may have not
been designed to support.
To avoid such a situation, the internal foldback point
correction circuit varies the VCS voltage limit according
to the bus voltage. This means the VCS will be
decreased when the bus voltage increases. To keep a
constant maximum input power of the converter, the
required maximum VCS versus various input bus
voltage can be calculated, which is shown in Figure 7.
1
typical maximum limit on VCS versus the ZC current is
shown in Figure 8.
1
0.9
0.8
0.7
0.6
300
500
700
900 1100 1300 1500 1700 1900 2100
Iz c (uA)
Figure 8
VCS-max versus IZC
0.9
0.8
0.7
0.6
80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400
Vin(V)
Figure 7 Variation of the VCS limit voltage according
to the IZC current
According to the typical application circuit, when
MOSFET is turned on, a negative voltage proportional
to bus voltage will be coupled to auxiliary winding.
Inside ICE2QS03G, an internal circuit will clamp the
voltage on ZC pin to nearly 0V. As a result, the current
flowing out from ZC pin can be calculated as
IZC
=
-V----B-----U----S----N-----a-
RZC1NP
[5]
When this current is higher than IZC_1, the amount of
current exceeding this threshold is used to generate an
offset to decrease the maximum limit on VCS. Since the
ideal curve shown in Figure 7 is a nonlinear one, a
digital block in ICE2QS03G is implemented to get a
better control of maximum output power. Additional
advantage to use digital circuit is the production
tolerance is smaller compared to analog solutions. The
3.5
Active Burst Mode Operation
At light load condition, the IC enters Active Burst Mode
operation to minimize the power consumption. Details
about Active Burst Mode operation are explained in the
following paragraphs.
3.5.1
Entering Active Burst Mode Operation
For determination of entering Active Burst Mode
operation, three conditions apply:
• the feedback voltage is lower than the threshold of
VFBEB(1.25V). Accordingly, the peak current sense
voltage across the shunt resistor is 0.17;
• the up/down counter is 7; and
• a certain blanking time (tBEB).
Once all of these conditions are fulfilled, the Active
Burst Mode flip-flop is set and the controller enters
Active Burst Mode operation. This multi-condition
determination for entering Active Burst Mode operation
prevents mistriggering of entering Active Burst Mode
operation, so that the controller enters Active Burst
Mode operation only when the output power is really
low during the preset blanking time.
3.5.2
During Active Burst Mode Operation
After entering the Active Burst Mode the feedback
voltage rises as VOUT starts to decrease due to the
inactive PWM section. One comparator observes the
feedback signal if the voltage level VBH (3.6V) is
exceeded. In that case the internal circuit is again
activated by the internal bias to start with swtiching.
Turn-on of the power MOSFET is triggered by the
timer. The PWM generator for Active Burst Mode
operation composes of a timer with a fixed frequency of
52kHz, typically, and an analog comparator. Turn-off is
resulted by comparison of the voltage signal v1 with an
internal threshold, by which the voltage across the
shunt resistor VcsB is 0.34V, accordingly. A turn-off can
also be triggered by the maximal duty ratio controller
which sets the maximal duty ratio to 50%. In operation,
Version 2.1
10
February 5, 2010
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